What an absolute monster of a thread... so forgive me if it has already been discussed but the search feature is not very helpful.
I ran into a mesecon issue in Minetest Extended so I posted there, and was kindly informed of the existence of this thread.
Basically, I've had heaps of fun playing with this mod and one thing leading to another, I've built a clock and two registers. However, the clock just stops from time to time because its FPGA overheats. I've added an extra delayer to my clock to slow it down, but it's kind of a bummer I have to half the frequency.
Would it help if I used standalone logic gates instead of a FPGA or will I still have intermittent faceplants down the line?
Now, to share the fun, here's the faulty clock:

And the two registers:

Thanks in advance!